EC 513 Computer Architecture - Spring 2018


Laboratory Exercises

There will be four laboratory assignments to explore the concepts taught in lecture using industrial strength tools (Pin):

The vehicle ISA for instroducing the architectural concepts in the class will be the RISC-V ISA.

Location: Photonics Center (PHO) 307

  • Laboratory 0 [pdf] Due: January 30th 2018
  • Laboratory 1 [pdf] Due: February 13th 2018
  • Laboratory 2 [pdf] Due: February 27th 2018
  • Laboratory 3 [pdf] Due: March 27th 2018
  • Class Project: In lecture, we have covered the key and time-tested concepts in computer architecture: pipelining, complex pipelining (Superscalar, Out-of-Order Execution, VLIW, Vector, Hardware Multi-threading, Branch Prediction, Speculative Execution, Caching, Memory Virtualization, Multi-core, etc.). All these concepts exploit one or more of these parallelism modalities: Instruction Level Parallelism (ILP), Data Level Parallelism (DLP) and Task Level Parallelism (TLP) to improve the cycle-per-instruction (CPI), a/the core processor performance measurement metric. In this project, you will select one of these concepts, implement it, and optimize it for hands-on architecture design trade-offs experience.

    RISC-V instruction set is recently proposed by a group of researchers at EECS Department of University of California, Berkeley. The RISC-V instruction set has been used by researchers to test architectures relating to memory and cache sub-systems, power and performance improvement, among others.

    To start off your design, we are providing you with the BRISC-V© single cycle processor base. BRISC-V© is part of the Heracles© design platform, an open-source, functional, parameterized, synthesizable research and teaching tool for architectural exploration and hardware-software co-design. It is an implementation of the RISC-V instruction set. An ISA recently proposed by a group of researchers at EECS Department of University of California, Berkeley. It has been used by researchers to test architectures relating to memory and cache sub-systems, power and performance improvement, among others. [pdf] Due: May 1st 2018