Many computer organization and computer architecture classes have recently started adopting the RISC-V architecture as an alternative to proprietary RISC ISAs and architectures. Simulators are a common teaching tool used to introduce students to writing assembly. We present the BRISC-V (Boston University RISC-V) Simulator and teaching tool, a RISC-V simulator inspired by existing RISC and CISC simulators. Our simulator is a web-based, pure javascript implementation meant to simplify deployment, as it does not require maintaining support for different OSs or any installation. Here we present the workings, usage, and extensibility of the BRISC-V simulator.

Example RISC-V Assembly Files:

  • gcd.s
  • fibonacci.s
  • binary_search.s

BRISC-V Simulator Tutorial

  • tutorial.pdf
  • tutorial.pptx

RISC-V Reference