EC 500 Hardware Security

Spring 2020


Course description

Hardware security sits at the intersection of cryptographic engineering and hardware design. It includes hardware-root-of-trust design techniques, access control, secure multi-party computation, code authenticity techniques, secure key storage, secure execution, side-channel analysis, obfuscation methods, and IC supply chain risks. The Course introduces students to these hardware security concepts through the design of a secure multi-core processor. Using an out-of-order RISC-V processor template, students examine micro-architecture side-channel vulnerabilities, defenses, and trusted execution extensions and micro-architecture modifications.

Objectives

The course will enhance students' preparation to identify, understand and potential propose hardware-as-root-of-trust solutions for the most pressing cyber security problems. Upon successful completion of this course, students will be able to:

  • distinguish between software and hardware security;
  • understand the potential of information leakage at microprocessors, memories and memory organizations, and on-chip networks levels;
  • evaluate computing system in terms of performance, reliability, and security;
  • effectively assess new hardware security approaches.

Textbook (No Textbook Required)

M. Tehranipoor and C. Wang, Introduction to Hardware Security and Trust, Springer, 2011 (Recommended)

Term Office Hours

  • Prof. Kinsy: PHO 335 - Tuesdays and Thursdays from 2:00PM to 3:00PM and by appointment.