EC 513 Computer Architecture - Spring 2018


Class Syllabus

The general format of the course consists of some regular lectures, discussion sections, problem sets, labs and a project.
Grading Policy
  • Participation: 5%
  • Laboratory Assignments: 35%
  • Project: 25%
  • Midterm Exam: 20%
  • Final Exam: 15%
  • Grades will be posted on Blackboard.
  • Grades will be assigned two ways:
    • >90 [A], >80 [B], >70 [C], >60 [D]
    • Curved according to the class median. Here your relative score is what really matters, rather than the objective scores above.
Missed Class Policy

Students must contact the instructor prior to missing an exam to schedule a makeup exam. Makeup exams will only be scheduled following an exam in cases of documented emergencies.

Late Submission Policy

Problem sets or laboratory assignments or course project submitted after the due date/time are considered late and will not be graded. Late submissions will only be graded in cases of documented emergencies.

Plagiarism

Discussion of course material and collaboration with other students is encouraged but each student must write/type and submit his/her own solution. Your essays, code and proofs (if applicable) should never contain sections which are identical to the submission of another student, past or present. Submitted work must be entirely that of the student(s) whose name(s) appear(s) on the submission and not solicited in any way from others. Violation of these policies can result in automatic failure of the course.

Please refer to the Boston University’s policy on academic dishonesty.
Tentative Schedule
Tuesday Thursday

Jan 16

Winter Recess

M. Kinsy

Jan 18 - L01

Influence of Technology and Software on Instruction Sets

M. Kinsy

Jan 23 - L02

Intel Pin introduction

Laboratory 0

M. Kinsy

Jan 25 - L03

Single-cycle ISA Implementation

M. Kinsy

Jan 30 - L04

Pipelining and Hazards

Laboratory 0 DUE

Laboratory 1

M. Kinsy

Feb 1 - L05

Hazard Resolution

M. Kinsy

Feb 6 - L06

Complex Pipelining: Superscalar

M. Kinsy

Feb 8 - L07

Complex Pipelining: VLIW

M. Kinsy

Feb 13 - L08

Branch Prediction

Laboratory 1 DUE

Laboratory 2

M. Kinsy

Feb 15 - L09

SIMD and Vector Processors

M. Kinsy

Feb 20

Virtual Monday

M. Kinsy

Feb 22 - L10

Multithreading

M. Kinsy

Feb 27 - L11

GPU Architectures

Laboratory 2 DUE

M. Kinsy

Mar 1

Midterm Exam

M. Kinsy

Mar 6

Spring Recess

M. Kinsy

Mar 8

Spring Recess

M. Kinsy

Mar 13 - L12

Snow Day

Laboratory 3

M. Kinsy

Mar 15 - L13

Cache Organization

M. Kinsy

Mar 20 - L14

Advanced Memory Operations

M. Kinsy

Mar 22 - L15

Modern Virtual Memory and Virtualization

M. Kinsy

Mar 27 - L16

Synchronization and Sequential Consistency

Laboratory 3 DUE

Mar 29 - L17

Cache Coherence - Snoopy Cache Coherence

M. Kinsy

Apr 3 - L18

Cache Coherence - Directory Cache Coherence

M. Kinsy

Apr 5 - L19

On-chip Network Architectures

Project Proposals DUE

M. Kinsy

Apr 10 - L20

On-chip Networking

M. Kinsy

Apr 12

Project Activities

M. Kinsy

Apr 17

Project Activities

M. Kinsy

Apr 19

Project Activities

Mid-Project Reports DUE

M. Kinsy

Apr 24

Project Activities

M. Kinsy

Apr 26

Project Activities

M. Kinsy

May 1

Project Presentations

Final Project Report DUE

May 3

Study Period

M. Kinsy

May 8

Final examinations

May 10

Final examinations

M. Kinsy