EC 700 Hardware and Systems Security

Fall 2018

Class Project

This class is hands-on and project focused. The class project is built around the RISC-V ISA. An initial multi-core, multi-threaded RISC-V architecture (in the Verilog RTL) will be made available to the class. Students will then research, select and implement a secure version of the architecture targeting a specific attack class. Specifically, students will:
  • Describe a relevant and pressing attack model;
  • Propose some architecture feature(s) to protect against the described attack;
  • Implement, test and validation of the security safeguard provided.