[ C16 ] X. Wang, B. Williams, J. D. Leidel, A. Ehret, M. Mark, M. A. Kinsy and Y. Chen: “xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing”, In the 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2021. [Paper] [BibTex]
Best Paper Award
[ C15 ] G. Dessouky, M. Isakov, M. A. Kinsy, P. Mahmoody, Miguel Mark, A. Sadeghi, E. Stapf, and S. Zeitouni: “Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures”, In the 58th ACM/EDAC/IEEE Design Automation Conference (DAC), 2021.[Paper] [BibTex]
[ J5 ] P. Yellu, L. Buell, M. Mark, M. Kinsy, D. Xu, Q. Yu: “Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-Architecture Perspectives”, Transactions on Design Automation of Electronic Systems (TODAES), In Press 2021.
[ C14 ] M. Isakov, E. del Rosario, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, and M. A. Kinsy: “HPC I/O Throughput Bottleneck Analysis with Explainable Local Models”, In the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2020.[Paper] [BibTex]
[ C13 ] X. Wang, B. Williams, J. D. Leidel, A. Ehret, M. A. Kinsy and Y. Chen: “Remote Atomic Extension (RAE) for Scalable High Performance Computing”, In the 57th ACM/EDAC/IEEE Design Automation Conference (DAC), 2020.[Paper] [BibTex]
[ C12 ] R. Agrawal, L. Bu, and M. A. Kinsy: “A Post-Quantum Secure Discrete Gaussian Noise Sampler”. In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2020.[Paper] [BibTex]
[ C11 ] R. Agrawal, L. Bu, E. del Rosario and M. A. Kinsy: “Design-flow Methodology for Secure Group Anonymous Authentication”. In the Design, Automation and Test in Europe Conference (DATE), 2020.[Paper] [BibTex]
[ C10 ] R. Agrawal, L. Bu, A. Ehret, and M. A. Kinsy: “Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives”. In the International conference on Field Programmable Logic and Applications (FPL), 2019.[Paper] [BibTex]
[ J5 ] E. Taheri, M. Isakov, A. Patooghy, M. A. Kinsy: “Addressing a New Class of Reliability Threats in 3-Dimensional Network-on-Chips”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.[Paper] [BibTex]
[ J4 ] T. Yang, Y. Wei, Z. Tu, H. Zeng, M. A. Kinsy, N. Zheng and P. Ren: “Design Space Exploration of Neural Network Activation Function Circuits”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.[Paper] [BibTex]
[ C9 ] J. R. Doppa, R. G. Kim, M. Isakov, M. A. Kinsy, H. Kwon and T. Krishna: “Adaptive Manycore Architectures for Big Data Computing.” In the International Symposium on Networks-on-Chip (NOCS), October 2017.[Paper] [BibTex]
[ C8 ] M. Kinsy, S. Khadka, M. Isakov and A. Farrukh: “Hermes: Secure Heterogeneous Multicore Architecture Design.” In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.[Paper] [BibTex]
[ J3 ] P. Ren, M. Kinsy, and N. Zheng: “Fault-Aware Load-Balancing Routing for 2D-Mesh and
Torus On-Chip Network Topologies.” In the Transactions on Computers (TC), March 2016.[Paper] [BibTex]
[ J2 ] P. Ren, X. Ren, S. Sane, M. Kinsy, and N. Zheng: “Deadlock-Free and Connectivity-
Guaranteed Methodology for Achieving Fault-tolerance in On-chip Networks.” In the Transactions
on Computers (TC), February 2016.[Paper] [BibTex]
[ J1 ] M. Kinsy, M. H. Cho, T. Wen, M. Lis , G. E. Suh, M. Dijk, and S. Devadas: “Optimal and
Heuristic Application-Aware Oblivious Routing.” In the Transactions on Computers (TC),
January 2013.[Paper] [BibTex]
[ C7 ] M. Kinsy, I. Celanovic, O. Khan, and S. Devadas: “MARTHA: Architecture for Control and
Emulation of Power Electronics and Smart Grid Systems.” In IEEE International Conference
on Design, Automation and Test in Europe (DATE), March, 2013.[Paper] [BibTex]
[ C6 ] M. Kinsy, M. Pellauer, and S. Devadas: “Heracles: Fully Synthesizable Parameterized
MIPS-Based Multicore System.” In Proceedings of the 21st International Conference on
Field Programmable Logic and Applications (FPL), September 2011.[Paper] [BibTex]
Tools and Open-Source Community Service Award
[ C5 ] M. Pellauer, M. Adler, M. Kinsy, A. Parashar, and J. Emer: “HAsim: FPGA-based highdetail
multicore simulation using time-division multiplexing.” In Proceedings of the 17th
International Symposium on High Performance Computer Architecture (HPCA), February
2011.[Paper] [BibTex]
[ C4 ] M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas: “Oblivious Routing in
On-Chip Bandwidth-Adaptive Networks.” In Proceedings of the Parallel Architectures and
Compilation Techniques (PACT), September 2009.[Paper] [BibTex]
[ C3 ] M. Kinsy, M. H. Cho, T. Wen, G. E. Suh, M. Dijk, and S. Devadas: “Application-Aware
Deadlock-Free Oblivious Routing.” In Proceedings of the International Symposium on Computer
Architecture (ISCA), June 2009.[Paper] [BibTex]
[ C2 ] K. S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis , G. E. Suh, and S. Devadas: “A
Comparison of Static and Dynamic Virtual Channel Allocation in Oblivious Routing.” In
Proceedings of the International Symposium on Networks-on-Chip (NOCS), May 2009.[Paper] [BibTex]
[ C1 ] M. H. Cho, C-C. Cheng, M. Kinsy, G. E. Suh, and S. Devadas: “Diastolic Arrays:
Throughput-Driven Reconfigurable Computing.” In Proceedings of the International Conference
on Computer-Aided Design (ICCAD), November 2008.[Paper] [BibTex]
