Class Syllabus

The general format of the course consists of some regular lectures, problem sets, labs, a project, and exams.

Grading Policy

• Grades will be posted on Canvas.
• Participation: 5%
• Laboratory Assignments: 65%
• Midterm Exam: 15%
• Final Exam: 15%
• Grades will be assigned two ways:
  • >90 [A], >80 [B], >70 [C], >60 [D]
  • Curved according to the class median. Here your relative score is what really matters, rather than the objective scores above.

Late Submission Policy

Problem sets or laboratory assignments or course project submitted after the due date/time are considered late and will not be graded. Late submissions will only be graded in cases of documented emergencies.

Plagiarism

Discussion of course material and collaboration with other students is encouraged but each student must write/type and submit his/her own solution. Your essays, code and proofs (if applicable) should never contain sections which are identical to the submission of another student, past or present. Submitted work must be entirely that of the student(s) whose name(s) appear(s) on the submission and not solicited in any way from others. Violation of these policies can result in automatic failure of the course.

Please refer to the Arizona State University’s policy on academic dishonesty.

Tentative Schedule

Monday	Wednesday
Jan 12 - Review Module - L01 History of Computer Systems Review Self-Assessment M. Kinsy	Jan 14 - Learning Module 1 - L02 Influence of Technology and Software on Instruction Sets Self-Assessment DUE Laboratory 0 M. Kinsy
Jan 19 Martin Luther King Jr. Day	Jan 21 - L03 Intel Pin introduction M. Kinsy
Jan 26 - L04 Single-cycle & Multi-cycle Architectures M. Kinsy	Jan 28 - L05 Preformance Evaluation Methodologies Laboratory 0 DUE Laboratory 1 M. Kinsy
Feb 02 - L06 Pipelining & Hazard Resolution M. Kinsy	Feb 04 - L07 Complex Pipelining: Superscalar M. Kinsy
Feb 09 - L08 Branch Prediction M. Kinsy	Feb 11 - L09 Complex Pipelining: VLIW Laboratory 1 DUE Laboratory 2 M. Kinsy
Feb 16 - L10 SIMD and Vector Processors M. Kinsy	Feb 18 - L11 Multithreading M. Kinsy
Feb 23 - L12 GPU Architectures	Feb 25 - L13 Dataflow & Systolic Architectures Laboratory 2 DUE M. Kinsy
Mar 02 - LR1 Review Lecture M. Kinsy	Mar 04 Midterm Exam M. Kinsy
Mar 09 No Class - Spring Break M. Kinsy	Mar 11 No Class - Spring Break M. Kinsy
Mar 16 - L14 Memory Organization Laboratory 3 M. Kinsy	Mar 18 - L15 Advanced Memory Operations M. Kinsy
Mar 23 - L16 Advanced Memory Technologies - PIM, NVM, etc. M. Kinsy	Mar 25 - L17 Modern Virtual Memory M. Kinsy
Mar 30 - L18 Process Synchronization M. Kinsy	Apr 01 - L19 Sequential Consistency Laboratory 3 DUE M. Kinsy
Apr 06 - L20 Cache Coherence - Snoopy Cache M. Kinsy	Apr 08 - L21 Cache Coherence - Directory Cache M. Kinsy
Apr 13 - L22 On-chip Interconnect Network M. Kinsy	Apr 15 - L23 Interconnect Networking Laboratory 3 DUE M. Kinsy
Apr 20 - L24 On-chip Interconnect Network M. Kinsy	Apr 22 - L25 2.5/3D Chips & Chiplet Architectures Laboratory 3 DUE M. Kinsy
Apr 27 - L26 Massively Parallel Architectures (MPP) M. Kinsy	Apr 29 - LR2 Review II M. Kinsy
May 4 Final Exams	May 6 Final Exams