CSE 520 Computer Architecture II - Spring 2026


Class Syllabus

The general format of the course consists of some regular lectures, problem sets, labs, a project, and exams.
Grading Policy
  • Grades will be posted on Canvas.
  • Participation: 5%
  • Laboratory Assignments: 65%
  • Midterm Exam: 15%
  • Final Exam: 15%
  • Grades will be assigned two ways:
    • >90 [A], >80 [B], >70 [C], >60 [D]
    • Curved according to the class median. Here your relative score is what really matters, rather than the objective scores above.
Late Submission Policy

Problem sets or laboratory assignments or course project submitted after the due date/time are considered late and will not be graded. Late submissions will only be graded in cases of documented emergencies.

Plagiarism

Discussion of course material and collaboration with other students is encouraged but each student must write/type and submit his/her own solution. Your essays, code and proofs (if applicable) should never contain sections which are identical to the submission of another student, past or present. Submitted work must be entirely that of the student(s) whose name(s) appear(s) on the submission and not solicited in any way from others. Violation of these policies can result in automatic failure of the course.

Please refer to the Arizona State University’s policy on academic dishonesty.
Tentative Schedule
Monday Wednesday

Jan 12 - Review Module - LR

History of Computer Systems Review

Self-Assessment

M. Kinsy

Jan 14 - Learning Module 1 - L01

Influence of Technology and Software on Instruction Sets

Self-Assessment DUE

Laboratory 0

M. Kinsy

Jan 19

Martin Luther King Jr. Day

Jan 21 - L02

Intel Pin introduction

M. Kinsy

Jan 26 - L03A

Single-cycle & Multi-cycle Architectures

M. Kinsy

Jan 28 - L03

Multi-cycle & Pipelining

Laboratory 0 DUE

Laboratory 1

M. Kinsy

Feb 02 - L4

Pipelining & Hazards

M. Kinsy

Feb 04 - L05

Hazard Resolution

M. Kinsy

Feb 09 - L06

Preformance Evaluation Methodologies

M. Kinsy

Feb 11 - L07

Branch Prediction

Laboratory 1 DUE

Laboratory 2

M. Kinsy

Feb 16 - L08

Complex Pipelining: Superscalar

M. Kinsy

Feb 18 - L09

Complex Pipelining: VLIW

M. Kinsy

Feb 23 - L10

SIMD and Vector Processors

Feb 25 - L11

Multithreading

Laboratory 2 DUE

M. Kinsy

Mar 02 - L12

GPU Architectures

M. Kinsy

Mar 04

Midterm Exam

M. Kinsy

Mar 09

No Class - Spring Break

M. Kinsy

Mar 11

No Class - Spring Break

M. Kinsy

Mar 16 - L13

Memory Organization

Laboratory 3

M. Kinsy

Mar 18 - L14

Advanced Memory Operations

M. Kinsy

Mar 23 - L15

Advanced Memory Technologies - PIM, NVM, etc.

M. Kinsy

Mar 25 - L16

Modern Virtual Memory

M. Kinsy

Mar 30 - L17

Process Synchronization

M. Kinsy

Apr 01 - L18

Sequential Consistency

Laboratory 3 DUE

M. Kinsy

Apr 06 - L19

Cache Coherence - Snoopy Cache

M. Kinsy

Apr 08 - L20

Cache Coherence - Directory Cache

M. Kinsy

Apr 13 - L21

On-chip Interconnect Network

M. Kinsy

Apr 15 - L22

Interconnect Networking

Laboratory 3 DUE

M. Kinsy

Apr 20 - L23

On-chip Interconnect Network

M. Kinsy

Apr 22 - L24

2.5/3D Chips & Chiplet Architectures

Laboratory 3 DUE

M. Kinsy

Apr 27 - L25

Massively Parallel Architectures (MPP)

M. Kinsy

Apr 29 - LR

Review II

M. Kinsy

May 4

Final Exams

May 6

Final Exams