BRISC-V Toolbox
The BRISC-V toobox is the Boston RISC-V architecture design exploration suite. BRISC-V is comprised of a number of different processor architectures, a simulator, and a visual verilog file generation tool, for education and research projects.

The Boston RISC-V Processor Set (BRISC-V) is a parameterized set of modules for design space exploration using RISC-V ISA based architectures. We call the full set of processors and tools to support them the tool box. Included with the BRISC-V Tool box are (i) numerious RISC-V cores with different levels of complexity (e.g., single-cycle core, multiple-cycle, and reconfigurable pipelined), (ii) a programmable memory system with reconfigurable multi-level cache subsystems, (iii) BRISC-V explorer which is GUI software support for selecting parameterized verilog and (iv) the BRISC-V simulator for software RISC-V instruction emulation. The toolbox provides an easy to use, open-source, parameterized, fully synthesizable, platform for students and researchers experimenting with the RISC-V ISA features to quickly bring up a complete and fully working architecture and start applying their own modifications.

The BRISC-V hardware is comprised of a number of different single-core and multi-core systems. Each hardware component of BRISC-V (the cores,and cache subsystem) is written in parameterized Verilog HDL modules, enabling architectural changes with parameter settings. The core types currently supported by BRISC-V include RV32I implementations of a small single cycle core, five and seven stage pipeline cores and a larger RV32I out-of-order core. The cache subsystem interface supports numerous memory hierarchy configurations. An arbitrary cache size, associativity and number of levels can be selected with module parameters.

Additionally the BRISC-V Explorer provides a user friendly way to choose parameters and visualize a BRISC-V system. The application runs in a browser allowing users to easily run it on Windows, Linux or Mac. In the BRISC-V Explorer, users can 1) select their desired core type, 2) enter parameters such as memory size for that core, and 3) configure cache parameters including block size and associativity. Once a user is sure of their processor and generates their design a verilog the explorer tool will generate a verilog design based around the users selections. From there its up to the users imagination on what to do with it.

Finally the BRISC-V Simulator visually shows the state of the processor at every instruction and allows for exploration of a compiled code behaving as expected. Being an in browser tool OS dependencies are avoided allowing for an easy, fast, and intuitive exploration. The register file, instruction break down, memory state and program list are all displayed as the program operates.

The BRISC-V Simulator+C has online C/C++ editor panel and compiler back-end.

Workshop on Computer Architecture Education (WCAE) 2019 Paper pdf

Inaugural RISC-V Summit Presentation slides



September 12th, 2021
Maintenance of the BRISC-V platform moved to Arizona State University and the ASCS Laboratory there.

June 24th, 2019
Sahan is presenting the educational version of the BRISC-V at ISCA Workshop on Computer Architecture Education (WCAE) 2019. It highlights keys aspects of the tool to aid in the teaching of computer organization and architecture courses.

February 10th, 2019
Presenting the BRISC-V at FPGA 2019. New set or memory organization hierarchy and network-on-chip were added.

Januray 29th, 2019
Introducing the latest version of the BRISC-V at BARC 2019.

December 3rd, 2018
Please check us out at the RISC-V Summit this week.

November 2th, 2018
EC700 Fall 2018 projects: Hardware-Assisted Control Flow Obfuscation for RISC-V, Multicore RISC-V Security Enhancement, RISC-V Return-oriented programming (ROP) Protection using last branch record (LBR), and Hardware Multithreading Cache-Based Side Channel Model.

October 29th, 2018
Donato and Sahan will be introducing the platform at the RISC-V Summit.

October 26th, 2018
Thanks for EC513 Spring 2018 students for their feedback on the development version.