SECRISC-V 2020

Co-located with ISPASS

The First International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).

ISPASS Conference: April 5-7, 2020 - Boston, Massachusetts, USA.


Breaking News - Keynote Speakers

Title: The SiFive Open Secure Platform Architecture

Abstract: The Open, Secure Platform Architecture of SiFive Shield Modern SoC's require a scalable open platform architecture to implement security. SiFive Shield is an open, secure platform architecture that enables whole-SoC security features and lifecycle management. SiFive WorldGuard is integral to flexible, scalable solution and offers a hardware-based multi-domain security solution that encompasses both single and multi-core applications, for both embedded and application processor uses. Integration of coresight compatible trace and debug rounds out a solution ready to integrate into your next SoC design.

Brief Bio: Dr. Shubu Mukherjee is SiFive’s Chief SOC Architect. Shubu is the winner of the ACM SIGARCH Maurice-Wilkes award, a Fellow of ACM, a Fellow of IEEE, and the author of the book, “Architecture Design for Soft Errors.” Shubu holds 60+ patents and has written over 50+ technical papers in top architecture conference and journals. Before joining SiFive in December 2019, Shubu worked at Marvell, Cavium, Intel, and Compaq for 21 years. He received his MS and Phd from the University of Wisconsin-Madison and his B.Tech., from the Indian Institute of Technology, Kanpur.

Title: RISCV Foundation Security Activities

Abstract: A Note from the Chair of the Security Standing Committee of the RISCV Foundation.

Brief Bio: Dr. Helena Handschuh is a Security Technologies Fellow at Rambus, Inc. Her research and responsibilities include managing the foundational security technologies team in charge of research in crypto and post-quantum crypto; research in power analysis and side-channel attacks and countermeasures; research in secure memories and Security IP creation overall. She was formerly a Technical Director of Cryptography Research, Inc. (part of Rambus), and Chief Technology Officer at Intrinsic-ID. She was also the manager of the Applied Cryptography and Security Group at Gemplus (now Gemalto/Thales). She authored more than 50 peer-reviewed papers and holds 20+ patents in the areas of security and cryptography. Dr. Handschuh earned an M.Sc. in networks and communication engineering from ENSTA, Paris and a Ph.D. in cryptography from the ENST, Paris.

Topics

Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" in standard IEEE two-column format (both blind and non-blind submission forms are accepted).

Deadlines