Important Update: Due to the continuing impact of the COVID-19 pandemic, the ISPASS 2020 conference and SECRISC-V 2020 workshop will be virtual events (August 23-25, 2020).

First International Workshop on Secure RISC-V Architecture Design Exploration (SECRISC-V'20)
seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).


Congratulations SECRISC-V 2020 Accepted Papers!

Preliminary Program

8:30–8:40
Welcome note by Dr. Michel A. Kinsy
8:40–9:25
Dr. Helena Handschuh
Keynote: A Note from the Chair of the Security Standing Committee of the RISCV Foundation
9:25–9:50
Kevin Cheang, Cameron Rasmussen, Dayeol Lee, David Kohlbrenner, Krste Asanovic and Sanjit Seshia
Verifying RISC-V Physical Memory Protection [Paper] [Presentation]
9:50–10:15
Markku-Juhani Saarinen
A Lightweight ISA Extension for AES and SM4 [Paper] [Presentation]
10:15–10:30
Coffee break
10:30–10:55
Alan Ehret, Margaret S. Bauman, Karen Gettings, Bruce Jordan and Michel A. Kinsy
A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices [Paper] [Presentation]
10:55–11:20
Ba-Anh Dao, Anh-Tien Le, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki and Cong-Kha Pham
Dynamic Frequency Scaling as a countermeasure against simple power analysis attack in RISC-V processors [Paper] [Presentation]
11:20–11:45
Emmanuel Stapf, Ghada Dessouky and Ahmad-Reza Sadeghi
Enclave Computing on RISC-V: A Brighter Future for Security? [Paper] [Presentation]
11:45–1:00
Lunch
1:00–1:45
Dr. Shubu Mukherjee
Keynote: The SiFive Open Secure Platform Architecture
1:45–2:10
Pantea Kiaei and Patrick Schaumont
Domain-Oriented Masked Instruction Set Architecture for RISC-V [Paper] [Presentation]
2:10–2:35
Steven Milburn
Protecting Processors from Software Exploitation Cyberattacks: RISC-V Sets the Stage for a Streamlined CoreGuard® Integration [Paper] [Presentation]
2:35–3:00
Samuel Lindemer, Gustav Midéus and Shahid Raza
Real-time Thread Isolation and Trusted Execution on Embedded RISC-V [Paper] [Presentation]
3:00–3:15
Coffee break
3:15–3:40
Eliakin del Rosario, Mihailo Isakov, and Michel A. Kinsy
Preventing Cache-Based Side-Channel Attacks with Obfuscating Cache Architectures [Paper] [Presentation]
3:40–4:10
Fumio Arakawa, Makoto Ikeda, Akira Tsukamoto and Kuniyasu Suzaki
Examination of applicability of RISC-V security specifications to low-end processors [Paper] [Presentation]
4:10–4:35
Mihailo Isakov
Secure RISC-V Architectures Design Space Exploration Using the BRISC-V Platform [Paper] [Presentation]
4:35–5:00
Closing remarks and feedback from attendees



Camera-ready version and presentation resources - [Latex Template] and [PowerPoint Template].

Please note that the paper must be submitted in PDF format. The content of the submission is limited to four (4) pages.