Course description

Performance metrics and analysis; instruction set architectures (RISC, CISC, VLIW); single-cycle and pipelined processor design; pipeline hazards and data forwarding; out-of-order execution; branch prediction; memory hierarchy; DRAM; cache design; virtual memory; and introduction to GPU architecture.

Enrollment Requirements

Prerequisite: CSE 320.

Course Objectives

This course covers the fundamentals of modern computer architecture, including:

• Performance metrics and analysis
• Instruction set architecture design (RISC, CISC, VLIW)
• Single-cycle and pipelined processor design, including hazards and data forwarding
• Out-of-order execution and branch prediction
• Memory hierarchy, DRAM, cache design, and virtual memory
• Introduction to GPU architecture and CUDA programming

Expected Learning Outcomes

Upon successful completion of this course, students will be able to:

• know key classes of computer architectures, and new trends and developments in computer architecture;
• clearly explain the importance of pipelining, instruction-level parallelism (ILP), out-of-order execution, branch prediction, and virtual memory;
• understand the performance metrics of microprocessors and memory organizations, including cache and DRAM design;
• evaluate the performance, reliability, and energy efficiency of an architecture;
• take advantage of instruction-level and data-level parallelisms for efficient high-performance program execution, including on GPUs via CUDA;
• engage in research in computer architecture.

Textbook

J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2017 (6th edition)

Term Office Hours

• Prof. Kinsy (Lead-Instructor): Tuesday 3:30pm - 4:30pm, and by appointment. Office: BYENG 390, part of the BYENG 395 Suite - STAM Center.
• Mishel Paul (Co-Instructor): Tuesday & Thursday 4:00pm - 5:00pm, and by appointment.
• Nges Njungle (Co-Instructor): Monday & Wednesday 4:00pm - 5:00pm, and by appointment.