CSE 420 Computer Architecture I - Spring 2022


Class Syllabus

The general format of the course consists of some regular lectures, problem sets, labs, a project, and exams.
Grading Policy
  • Grades will be posted on Canvas.
  • Participation: 10%
  • Midterm Exam: 20%
  • Laboratory-based grading track:
    • Laboratory Assignments: 55%
    • Final Exam: 15%
  • Project-based grading track:
    • Laboratory Assignments: 40%
    • Major Class Project: 30%
  • Grades will be assigned two ways:
    • >90 [A], >80 [B], >70 [C], >60 [D]
    • Curved according to the class median. Here your relative score is what really matters, rather than the objective scores above.
Missed Class Policy

Students must contact the instructor prior to missing an exam to schedule a makeup exam. Makeup exams will only be scheduled following an exam in cases of documented emergencies.

The ongoing global pandemic has been very disruptive and the situation is still highly fluid. We understand and will be very accomodating. Please note that any COVID-19 accommodations that you may need throughout the course of the semester are best discussed with medical documentation.

Late Submission Policy

Problem sets or laboratory assignments or course project submitted after the due date/time are considered late and will not be graded. Late submissions will only be graded in cases of documented emergencies.

Plagiarism

Discussion of course material and collaboration with other students is encouraged but each student must write/type and submit his/her own solution. Your essays, code and proofs (if applicable) should never contain sections which are identical to the submission of another student, past or present. Submitted work must be entirely that of the student(s) whose name(s) appear(s) on the submission and not solicited in any way from others. Violation of these policies can result in automatic failure of the course.

Please refer to the Arizona State University’s policy on academic dishonesty.
Tentative Schedule
Monday Wednesday

Jan 10 - Review Module - LR-1 / LR-5

Computer Organization Review

Self-Assessment

M. Kinsy

Jan 12 - Learning Module 1 - L01

Influence of Technology and Software on Instruction Sets

Self-Assessment DUE

Laboratory 0

M. Kinsy

Jan 17

Martin Luther King Jr. Holiday

M. Kinsy

Jan 19 - Learning Module 1 - L02

Intel Pin introduction

Laboratory 0 DUE

Laboratory 1

M. Kinsy

Jan 24 - Learning Module 2 - L03

Single-cycle ISA Implementation

M. Kinsy

Jan 26 - Learning Module 2 - L04

CPU Pipelining

M. Kinsy

Jan 31 - Learning Module 2 - L05

Structural, Data and Control Hazards

M. Kinsy

Feb 02 - Learning Module 2 - L06

Hazard Resolution

M. Kinsy

Feb 07 - Learning Module 2 - L07

Performance Analysis

M. Kinsy

Feb 09 - Learning Module 3 - L08

Branch Prediction

Laboratory 1 DUE

Laboratory 2

M. Kinsy

Feb 14 - L09

Complex Pipelining: Superscalar

M. Kinsy

Feb 16 - L10

Multithreading

M. Kinsy

Feb 21 - E01

Midterm Exam

Feb 23 - L11

Memory Organization I

M. Kinsy

Feb 28 - L12

Memory Organization II

M. Kinsy

Mar 02 - L13

Advanced Memory Operations

Laboratory 2 DUE

Laboratory 3

M. Kinsy

Mar 07

Spring Recess

Mar 09

Spring Recess

Mar 14 - L14

Process Synchronization I

M. Kinsy

Mar 16 - L15

Process Synchronization II

M. Kinsy

Mar 21 - L16

Sequential Consistency

M. Kinsy

Mar 23 - L17

Cache Coherence - Snoopy Cache

Laboratory 3 DUE

Laboratory 4/Project

M. Kinsy

Mar 28 - L18

Cache Coherence - Directory Cache

M. Kinsy

Mar 30 - L19

On-chip Network Architectures

M. Kinsy

Apr 04 - L20

On-chip Routing

M. Kinsy

Apr 06 - L21

Complex Pipelining: VLIW

Laboratory 4 DUE

Laboratory 5

Mid-Project Status

M. Kinsy

Apr 11 - L22

SIMD and Vector Processors

M. Kinsy

Apr 13 - L23

GPU Architectures

M. Kinsy

Apr 18 - L24

Lecture/Review

M. Kinsy

Apr 20

Lecture/Review

Laboratory 5 DUE

M. Kinsy

Apr 25

Lecture/Review

M. Kinsy

Apr 27

Lecture/Review

Project DUE

M. Kinsy

May 02

Final examinations

May 05

Final examinations