CSE 420 Fundamentals of Computer Architecture Fall 2026

Reading

Reading assignments are from Hennessy & Patterson, 6th ed. Chapter/appendix references are shown below. GPU/CUDA readings will be posted later.

Lecture Topic Reading
History of Computer Architecture App M: Historical Perspectives and References
Review: RISC-V ISA and Assembly Programming I App A: Instruction Set Principles
Review: RISC-V ISA and Assembly Programming II App A: Instruction Set Principles (cont.)
Influence of Technology and Software on ISA Design Ch 1: Fundamentals of Quantitative Design and Analysis
Instruction Set Architecture Design: RISC vs. CISC vs. VLIW App A; App H: VLIW and EPIC
Single-Cycle Processor Design I App C: Pipelining: Basic and Intermediate Concepts
Single-Cycle Processor Design II App C (cont.)
Multi-Cycle Processor Design I App C (cont.)
Multi-Cycle Processor Design II App C (cont.)
Pipelined Processor Design I App C (cont.)
Pipelined Processor Design II App C (cont.)
Pipeline Hazards: Structural, Data, and Control App C (cont.)
Data Forwarding and Hazard Resolution App C (cont.)
Branch Prediction Ch 3: Instruction-Level Parallelism and Its Exploitation
Prefetching Ch 2: Memory Hierarchy Design
Out-of-Order Execution Ch 3; App C
Memory Hierarchy Fundamentals Ch 2: Memory Hierarchy Design
Cache Design I: Principles and Policies Ch 2; App B: Review of Memory Hierarchy
Cache Design II: Advanced Cache Operations Ch 2; App B
Virtual Memory Ch 2; App B
Instruction-Level Parallelism - VLIW App H: Hardware and Software for VLIW and EPIC
Thread-Level Parallelism Ch 5: Thread-Level Parallelism
GPU Architecture I: The SIMT Execution Model Ch 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures
GPU Architecture II: GPU Memory Hierarchy Ch 4 (cont.)
CUDA Programming I: Programming Model and Kernels Ch 4 (cont.); supplemental CUDA programming guide
CUDA Programming II: Optimization Techniques TBD - supplemental CUDA programming guide