The ASCS Laboratory is now part of the Secure, Trusted, and Assured Microelectronics (STAM) Center in the Ira A. Fulton Schools of Engineering at Arizona State University
Latest Publications (2022)
[ C ] M. Isakov and M. Kinsy: “SparseFabric: Ideal Topologies for Training Sparse Networks”, In the 40th IEEE International Conference on Computer Design (ICCD), 2022.
[ C ] J. Abraham, A. Ehret, and M. Kinsy: “A Compiler for Transparent Namespace-Based Access Control for the Zeno Architecture”, In the 2022 IEEE International Symposium onSecure and Private Execution Environment Design (SEED), 2022.
[ C ] M. Isakov, M. Currier, E. del Rosario, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, G. K. Lockwood, and M. A. Kinsy: “A Taxonomy of Error Sources in HPC I/O Machine Learning Models”, In the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2022.
Secure Computer Architectures
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2021[ C6 ] G. Dessouky, M. Isakov, M. A. Kinsy, P. Mahmoody, Miguel Mark, A. Sadeghi, E. Stapf, and S. Zeitouni: “Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures”, In the 58th ACM/EDAC/IEEE Design Automation Conference (DAC), 2021. [Paper] [BibTex] 2020[ J1 ] S. Bandara and M. A. Kinsy: “Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks”. Journal of Cryptographic Engineering, Springer, 2020. [Paper] [BibTex] 2019[ C5 ] S. Bandara and M. A. Kinsy: “Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks”. In 3rd Attacks and Solutions in Hardware Security Workshop (ASHES), 2019.[Paper] [BibTex] [ C4 ] M. Kinsy and N. Boskov: “Secure Computing Systems Design Through Formal Micro-Contracts”. In the 29th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2019.[Paper] [BibTex] [ W3 ] N. Boškov, M. Isakov and M. A. Kinsy: “CodeTrolley: Hardware-Assisted Control Flow Obfuscation”. Boston Area Architecture 2019 Workshop (BARC19), 2019.[Paper] [BibTex] [ W2 ] M. Graziano, M. Mark, S. Gvozdenovic and M. A. Kinsy: “Hardware Assisted Transparent ROP Mitigation for RISC-V”. Boston Area Architecture 2019 Workshop (BARC19), 2019.[Paper] [BibTex] 2018[ J1 ] M. A. Kinsy, L. Bu, M. Isakov and M. Mark: “Designing Secure Heterogeneous Multicore Systems from Untrusted Components”. Cryptography, vol. 2, iss. 3, no. 12, 2018.[Paper] [BibTex] [ C3 ] L. Bu, M. Mark and M. Kinsy: “A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.[Paper] [BibTex] [ W1 ] M. A. Kinsy, D. Kava, A. Ehret and M. Mark: “Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation”. Boston Area Architecture 2018 Workshop (BARC18), 2018.[Paper] [BibTex] 2017[ C2 ] H. Hosseinzadeh, M. Isakov, M. Darabi, A. Patooghy, and M. Kinsy: “Janus: An uncertain cache architecture to cope with side channel attacks”. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2017.[Paper] [BibTex] The Myril B. Reed Best Paper Award [ C1 ] M. Kinsy, S. Khadka, M. Isakov and A. Farrukh: “Hermes: Secure Heterogeneous Multicore Architecture Design”. In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.[Paper] [BibTex] |
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Post-Quantum Security
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2021[ B1 ] M. A. Kinsy: “Post-quantum Cryptographic Hardware Primitives”, In: Jajodia S., Samarati P., Yung M. (eds) Encyclopedia of Cryptography, Security and Privacy. Springer, Berlin, Heidelberg, 2021. [Paper] [BibTex] 2020[ C3 ] R. Agrawal, L. Bu, and M. A. Kinsy: “Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design”. In the 38th IEEE International Conference on Computer Design (ICCD), 2020. [Paper] [BibTex] Best Paper in the Test, Verification and Security Track [ R1 ] R. Agrawal, L. Bu, A. Ehret, and M. A. Kinsy: “Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption”. arXiv:2007.01648, 2020.[Paper] [BibTex] Report. [ C2 ] R. Agrawal, L. Bu, and M. A. Kinsy: “A Post-Quantum Secure Discrete Gaussian Noise Sampler”. In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2020.[Paper] [BibTex] [ P1 ] R. Agrawal, L. Bu, and M. A. Kinsy: “Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption”. In the 28th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), 2020.[Paper] [BibTex] 2019[ C1 ] R. Agrawal, L. Bu, A. Ehret, and M. A. Kinsy: “Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives”. In the International conference on Field Programmable Logic and Applications (FPL), 2019.[Paper] [BibTex] [ W2 ] L. Bu, R. Agrawal, H. Cheng and M. A. Kinsy: “A Lightweight McEliece Cryptosystem Co-Processor Design”. Boston Area Architecture 2019 Workshop (BARC19), 2019.[Paper] [BibTex] [ W1 ] L. Bu, R. Agrawal, H. Cheng and M. A. Kinsy: “Post-Quantum Cryptographic Hardware Primitives”. Boston Area Architecture 2019 Workshop (BARC19), 2019.[Paper] [BibTex] |
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Hardware Security
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2020[ C12 ] R. Agrawal, L. Bu, E. del Rosario and M. A. Kinsy: “Towards Programmable All-Digital True Random Number Generators”. In the 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020.[Paper] [BibTex] Best Paper Award [ C11 ] R. Agrawal, L. Bu, E. del Rosario and M. A. Kinsy: “Design-flow Methodology for Secure Group Anonymous Authentication”. In the Design, Automation and Test in Europe Conference (DATE), 2020.[Paper] [BibTex] [ C10 ] A. Ehret, K. M. Gettings, B. R. Jordan Jr. and M. A. Kinsy: “A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices”. In the 2020 IEEE High Performance Extreme Computing Conference (HPEC), 2020.[Paper] [BibTex] Outstanding Student Paper Award [ C9 ] V. Gadepally, M. Isakov, R. Agrawal, J. Kepner, K. M. Gettings and M. A. Kinsy: “Homomorphic Encryption Based Secure Sensor Data Processing”. In the 2019 IEEE High Performance Extreme Computing Conference (HPEC), 2020.[Paper] [BibTex] 2019[ C8 ] A. Ehret, K. M. Gettings, B. R. Jordan Jr. and M. A. Kinsy: “A Survey on Hardware Security Techniques Targeting Low-Power SoC Designs”. In the 2019 IEEE High Performance Extreme Computing Conference (HPEC), 2019.[Paper] [BibTex] [ C7 ] P. Yellu, N. Boskov, M. A. Kinsy and Q. Yu: “Security Threats in Approximate Computing Systems”. In the 29th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2019.[Paper] [BibTex] 2018[ J6 ] L. Bu, M. Isakov and M. A. Kinsy: “RASSS: A Hijack-resistant Confidential Information Management Scheme for Distributed Systems”. In the Institution of Engineering and Technology (IET), - Computers and Digital Techniques, 2018.[Paper] [BibTex] [ J5 ] L. Bu, M. Karpovsky and M. A. Kinsy: “Bulwark: Securing Implantable Medical Devices Communication Channels”. In the Elsevier Journal of Computers and Security (Computers & Security), 2018.[Paper] [BibTex] [ J4 ] L. Bu, M. Karpovsky and M. A. Kinsy: “Design of Reliable Storage and Compute Systems with Lightweight Group Testing Based Non-Binary Error Correction Codes”. In the Institution of Engineering and Technology (IET), - Computers and Digital Techniques, 2018.[Paper] [BibTex] [ J3 ] L. Bu, J. Dofe, Q. Yu and M. A. Kinsy: “SRASA: A Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems”. In the Journal of Hardware and Systems Security (HaSS), 2018.[Paper] [BibTex] [ J2 ] S. M. Sebt, A. Patooghy, H. Beitollahi and M. A. Kinsy: “Circuit Enclaves Susceptible to Hardware Trojans Insertion at Gate-Level Designs”. In the Institution of Engineering and Technology (IET), - Computers and Digital Techniques, 2018.[Paper] [BibTex] [ J1 ] L. Bu, M. Isakov, and M. A. Kinsy: “A Secure and Robust Scheme for Sharing Confidential Information in IoT Systems”. In the Elsevier Journal for Ad Hoc Networks, (Ad Hoc Networks), 2018.[Paper] [BibTex] [ C6 ] L. Bu, H. Cheng, and M. A. Kinsy: “Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems”. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 8-10, 2018.[Paper] [BibTex] [ C5 ] L. Bu, H. Cheng, and M. A. Kinsy: “Adaptive and Dynamic Device Authentication Based on Lorenz Chaotic Systems”. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2018.[Paper] [BibTex] [ C4 ] L. Bu and M. Kinsy: “Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions”. In the International conference on Field Programmable Logic and Applications (FPL), 2018.[Paper] [BibTex] [ C3 ] E. Aerabi, A. Patooghy, H. Rezaei, M. Mark, M. Fazeli and M. Kinsy: “Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.[Paper] [BibTex] [ C2 ] L. Bu and M. Kinsy: “Hardening AES Hardware Implementations Against Fault and Error Inject Attacks”. In the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2018.[Paper] [BibTex] 2017[ C1 ] L. Bu, H. D. Nguyen, and M. A. Kinsy: “RASSS: A perfidy-aware protocol for designing trustworthy distributed systems”. In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 23-25, 2017.[Paper] [BibTex] Best Student Paper Award and Best Paper Nominee |
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Neural Network Acceleration & Security
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2019[ C5 ] M. Isakov, V. Gadepally, K. M. Gettings and M. A. Kinsy: “A Survey of Attacks and Defenses of Edge-Deployed Neural Networks”. In the 2019 IEEE High Performance Extreme Computing Conference (HPEC), 2019.[Paper] [BibTex] Best Student Paper Finalist [ P1 ] M. Isakov and M. A. Kinsy: “NeuroFabric: A Priori Sparsity for Training on the Edge”. In the 2019 tinyML Summit (tinyML), 2019.[Paper] [BibTex] 2018[ C4 ] M. Isakov, L. Bu, H. Cheng, and M. A. Kinsy: “Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators”. In the 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2018.[Paper] [BibTex] [ J1 ] T. Yang, Y. Wei, Z. Tu, H. Zeng, M. A. Kinsy, N. Zheng and P. Ren: “Design Space Exploration of Neural Network Activation Function Circuits”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.[Paper] [BibTex] [ C3 ] M. Isakov and M. A. Kinsy: “NoSync: Particle Swarm Inspired Distributed DNN Training”. In the 27th International Conference on Artificial Neural Networks (ICANN), 2018.[Paper] [BibTex] [ C2 ] M. Isakov, A. Ehret and M. Kinsy: “Chameleon: A Generalized Reconfigurable Open-Source Architecture for Deep Neural Network Training”. In the 2018 IEEE High Performance Extreme Computing Conference (HPEC), 2018.[Paper] [BibTex] Best Student Paper Nominee [ C1 ] M. Isakov, A. Ehret and M. Kinsy: “ClosNets: Batchless DNN Training with On-Chip A Priori Sparse Neural Topologies”. In the International conference on Field Programmable Logic and Applications (FPL), 2018.[Paper] [BibTex] [ W1 ] M. Isakov and M. A. Kinsy: “ClosNets: a Priori Sparse Topologies for Faster DNN Training”, Boston Area Architecture 2018 Workshop (BARC18), 2018.[Paper] [BibTex] |
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On-chip Interconnection Networks
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2019[ J1 ] E. Taheri, M. Isakov, A. Patooghy, M. A. Kinsy: “Addressing a New Class of Reliability Threats in 3-Dimensional Network-on-Chips”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.[Paper] [BibTex] 2018[ C5 ] S. Kashi, A. Patooghy, D. Rahmati, M. Fazeli and M. A. Kinsy: “Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.[Paper] [BibTex] 2017[ C4 ] K. Soleimani, A. Patooghy, N. Soltani, L. Bu, and M. Kinsy: “Crosstalk Free Coding Systems to Protect NoC Channels Against Crosstalk Faults”. In 2017 IEEE 35th International Conference on Computer Design (ICCD) Nov 2017.[Paper] [BibTex] [ C3 ] E. Taheri, M. Isakov, A. Patooghy, and M. Kinsy: “Advertiser Elevator: a Fault Tolerant Routing Algorithm for Partially Connected 3D Network-on-Chips”. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2017.[Paper] [BibTex] [ C2 ] M. Kinsy, S. Khadka and M. Isakov: “PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures”. In the 27th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2017.[Paper] [BibTex] [ R1 ] P. Ren, M. Kinsy, M. Zhu, S. Khadka, M. Isakov, A. Ramrakhyani, T. Krishna, and N. Zheng. “FASHION: Fault-Aware Self-Healing Intelligent On-chip Network”. arXiv:1702.02313, 2017.[Paper] [BibTex]Report 2016[ C1 ] P. Ren, M. Kinsy, M. Zhu and N. Zheng: “Towards Connectivity-Guaranteed Power-gating Large-scale On-chip Networks”. The 7th International Green and Sustainable computing conference (IGSC), Nov 7-9, 2016.[Paper] [BibTex] |
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Adaptive-Approximate Architecture
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2021[ J1 ] P. Yellu, L. Buell, M. Mark, M. Kinsy, D. Xu, Q. Yu: “Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-Architecture Perspectives”, Transactions on Design Automation of Electronic Systems (TODAES), In Press 2021. [Paper] [BibTex] 2018[ W2 ] M. A. Kinsy, M. Isakov, A. Ehret and D. Kava: “SAPA: Self-Aware Polymorphic Architecture”, Boston Area Architecture 2018 Workshop (BARC18), 2018.[Paper] [BibTex] 2017[ C1 ] J. R. Doppa, R. G. Kim, M. Isakov, M. A. Kinsy, H. Kwon and T. Krishna: “Adaptive Manycore Architectures for Big Data Computing”. In the International Symposium on Networks-on-Chip (NOCS), October 2017.[Paper] [BibTex] [ W1 ] R. S. Agrawal and M. A. Kinsy: “Adaptive-Approximate Cache Architecture”. In the 3rd Career Workshop for Women and Minorities in Computer Architecture, held in conjunction with the 50th IEEE/ACM International Symposium on Microarchitecture (MICRO-50), October, 2017. [ T1 ] Rashmi S. Agrawal: “Adaptive-Approximate Cache Architecture”, M.S. Project, September, 2017. |
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Graph Processor Design
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Domain Specific Architectures
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2021[ C ] X. Wang, B. Williams, J. D. Leidel, A. Ehret, M. Mark, M. A. Kinsy and Y. Chen: “xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing”, In the 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2021. Best Paper Award[Paper] [BibTex] 2019[ P1 ] M. Mark, D. Whelihan, M. Vai, H. Whitman and M. A. Kinsy: “Resilience-Aware Decomposition and Monitoring of Large-Scale Embedded Systems”. In the 2019 IEEE High Performance Extreme Computing Conference (HPEC), 2019.[Paper] [BibTex] 2018[ C2 ] A. Ehret, M. Isakov and M. A. Kinsy: “Towards a Generalized Reconfigurable Agent Based Architecture: Stock Market Simulation Acceleration”, International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2018.[Paper] [BibTex] [ C1 ] A. Ehret, P. Jamieson and M. A. Kinsy: “Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations”, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2018.[Paper] [BibTex] Released SoftwareLink to the project home page [Link] |
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Architecture Design Space Exploration Tools
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2022[ C4 ] M. Isakov, M. Currier, E. del Rosario, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, G. K. Lockwood, and M. A. Kinsy: “A Taxonomy of Error Sources in HPC I/O Machine Learning Models”, In the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2022.[Paper] [BibTex] 2020[ C3 ] M. Isakov, E. del Rosario, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, and M. A. Kinsy: “HPC I/O Throughput Bottleneck Analysis with Explainable Local Models”, In the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2020.[Paper] [BibTex] [ W3 ] E. del Rosario, M. Currier, Mihailo Isakov, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, K. Harms, S. Snyder, and M. A. Kinsy: “Gauge: An Interactive Data-Driven Visualization Tool for HPC Application I/O Performance Analysis”, In the 5th International Parallel Data Systems Workshop (PDSW 2020) at SC20.[Paper] [BibTex] [ W2 ] M. Isakov, E. del Rosario, S. Madireddy, P. Balaprakash, P. H. Carns, R. Ross, and M. A. Kinsy: “Towards Generalizable Models of I/O Throughput”, In the 10th International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2020) at SC20. [Paper] [BibTex] [ C2 ] X. Wang, B. Williams, J. D. Leidel, A. Ehret, M. A. Kinsy and Y. Chen: “Remote Atomic Extension (RAE) for Scalable High Performance Computing”, In the 57th ACM/EDAC/IEEE Design Automation Conference (DAC), 2020.[Paper] [BibTex] 2019[ W1 ] R. Agrawal, S. Bandara, A. Ehret, M. Isakov, M. Mark, and M. A. Kinsy: “The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture”, In Workshop on Computer Architecture Education (WCAE), 2019.[Paper] [BibTex] [ C1 ] S. Bandara, A. Ehret, D. Kava and M. A. Kinsy: “BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox”, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2019.[Paper] [BibTex] 2018[ S1 ] D. Kava, S. Bandara, M. A. Kinsy: “Architecture Design Space Exploration Using RISC-V”. In the Inaugural RISC-V Summit Proceedings (RISC-V Summit), December 2018.[Paper] [BibTex] |
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