Notes on the latest stable release (Heracles 2.0) is on the Wiki page.

In the latest stable release, there are three units:

GUI for the complete system for a quick system generation.
Heracles Designer installation directory contains the following relevant folders:

  - applications: it contains few program examples and their binaries.
  - configurations: it is meant to hold saved systems configurations. It comes with two test cases.
  - userSystemRTL: it is meant to hold automatically generated system configuration Verilog files.
  - softwareToolchain: it has the compiler files (It's the folder that should be copied into the Linux environment for compilation).
  - sourceCode: it holds the different Verilog modules to be used to build a user defined system configuration.
  - targetPlatformEnv: it contains critical files to automatically runtime environment (ModelSim is the current target).

Heracles Hardware (Verilog code)
It contains the different Verilog modules to be used to build a user defined system configuration.

  - modules: this folder has 4 subfolders injector_core, memory, mips_core, and router folders.

is the injector core, it does no useful computation, it just injects packet into the network. This function is very useful when one is focusing on the network on-chip behavior. Also it can be used to saturate easily the network where it is difficult to find a good application running on real core.

        Dummy_Node: the injector attached to a router.
        Dummy_Cores_Mesh: is the 2-D mesh of injector cores.
the direct mapped cache unit.
        Main_Memory: main memory block unit.
        Mem_System_Wrapper: it has local memory and network interface unit.
        MemoryRouterSystem: memory-router unit.
        Packetizer: there are three sub-modules defined in Packetizer_helpers and Packetizer_Lite files.
       Packetizer_helpers: it has the local memory interface unit that acts as a third cache on the local memory side, and the local cache system interface unit that uses a memory-like protocol to interact with the cache system like a second larger memory block.
        Packetizer_Lite: it directly connects to the network router. it is responsible for converting data traffic, such as a load, coming from the local memory and the cache system into packets or flits that can be routed inside the Network on-chip (NoC), and for reconstructing packets or flits into data traffic at the opposite side when exiting the NoC.
        unified_caches: is a simple wrapper that contains both instruction cache and data cache.

the arithmetic logic unit
        decode: the decoder
        regFile: the register file
        7_Stage_MIPS_Core: the integer-based seven-stage MIPS Core
        Real_Cores_Mesh: is the 2-D mesh of MIPS cores.

is the routing arbiter, it does a round-robin arbitration, but it also adjusts priorities to promote good throughput and fairness.
        buffer_port: a port has input bus, an array of fifo and an output bus.
        crossbar: crossbar unit.
        fifo: fifo unit.
        router: the router module, the routing operation takes four steps or phases, namely routing (RC), virtual-channel allocation (VA), switch allocation (SA), and switch traversal (ST), where each phase corresponds to a pipeline stage in the router.
  - testbench: It has the top level testbench file and a reference folder which contains system wrappers that user can change to generate manually and run configurations without the GUI.

Software to programming the cores (MIPS Linux-based cross compiler)
The two relevant files here that user can modified are linker.cpp and isa-checker.cpp.

  - isa-checker its role is to: (1) remove all memory space primitives, (2) replace all pseudo-instructions, and (3) check for floating point instructions.
  - linker: it adds a small kernel-like binary code to the application binary code for memory space management and workload distribution. User can modify the linker.cpp file provided in the toolchain to reconfigure the memory space and workload.

Next release items
These modules are implemented and are currently being tested:
- Remote access cache coherence scheme
- Two hardware threaded MIPS core
- Set associated cache

We are still looking into how to best address these items:
- Connect the GUI to the software compiler directly.
- Flexible automatic setup of FPGA environment.