Heracles Project
Heracles is a complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies, sizes, and memory configurations.

Multicore architectures have become mainstream computing platforms. These systems typically consist of processing elements (PEs or cores), a memory subsystem, and an infrastructure for inter-core communications. Traditionally, buses have been used in establishing communications between cores, but because of the increasing complexity of these designs and the lack of scalability of wired connections between cores, network-on-chip (NoC) architectures have been introduced as
an effective data communication infrastructure. It has been shown that the overall performance of multicore systems is often defined by their communication limits in terms of bandwidth, speed and concurrency, and not by the individual computation power of the cores. Therefore, simple reduced instruction set computer (RISC) cores are often used in these architectures.

There has been a large body of work on implementing multicore architectures on FPGAs. In contrast, there seems to be very little on complete, modular, multicore systems, with reconfigurable network topology, where processing core, memory system, and on-chip network are fully self-contained.

Heracles presents designers with a global and complete view of the inner workings of a multiprocessor machine cycle-by-cycle from instruction fetches at the microprocessor core at each node to the flit arbitration at the routers, with RTL level correctness. A flit is the smallest unit of information recognized by the flow control method. This enables the designer to explore different implementation approaches: core microarchitecture, levels of caches, cache sizes, routing algorithm, router micro-architecture, distributed or shared memory, or network interface, and to quickly evaluate their impact on the overall system performance.

Fully functional, synthesizable, multicore system is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. Without loss in timing accuracy and logic, complete systems can be constructed, simulated or synthesized onto an FPGA, with minimal effort. Heracles is designed with a high degree of modularity to support exploration of future multicore processors of different topologies, routing schemes, processing elements or cores, and memory system organizations. It has a compiler toolchain for mapping C or C++ based applications onto the core units. The graphical user interface, allows the user to quick configure and launch a system instance.


October 30th, 2018
We have decided to make the RISC-V development its own branch to simplify the compilation process.

May 22th, 2018
Heracles 3.0 will support a suite of RISC-V development cores.

August 4th, 2016
The maintenance and development of the Heracles project will now be done through the Adaptive and Secure Computing Systems (ASCS) Laboratory at Boston University.

December 30th, 2013
Latest version of Heracles 2.0 is now live.

June 15th, 2013
Heracles 2.0 is now available with more advanced programming constructs.

March 30th, 2013
Heracles 2.0 will be available soon.

May 23rd, 2012
Remote access (RA) caching protocol is now available on Heracles.